The present invention relates in general to data processing systems, and in particular, functional testing of data processing devices.
Functional testing of a data processing device, typically a microprocessor or microcontroller, entails driving a set of pattern lines on a selected pin or alternatively a set of pins of the device. (This set of lines may also be referred to as a pattern.) Each pattern line (or, equivalently, vector) contains a sequence of binary values. Each sequence of binary values includes an input portion and an output portion. The input portion constitutes the binary sequence driven on the pins under test, and the output portion contains the sequence of output values expected on a corresponding output pin. The sets of pattern lines are generated to exercise a particular architectural element in the device under test (DUT). The generation of pattern lines to effect a particular test is not germane to the present invention, and will be presumed to be specified in accordance with the practice in the art.
Typically, a region in the device operating parameter space exists for which the architectural element being exercised will perform correctly, and beyond which the element fails. Generally, the parameter space of interest is clock speed and operating voltage. For a given clock speed, a device usually will fail as the operating voltage decreases. In other words, a microprocessor, for example, can be operated at higher clock speeds if the supply voltage is increased. Likewise, for a fixed supply voltage, the device typically fails as the clock speed is increased. Furthermore, increasing the clock speed or the operating voltage increases the power dissipated by the device, and concomitantly, the heating of the device. As the device, or the element being exercised heats up, the transistors in the device slow down. Consequently, as the device heats, failures maybe expected to occur. Thus, as the patterns are repeated over a region in the two-dimensional voltage-speed parameter space, a locus of points is generated (i.e., a speed path failure curve) that delimits the error free operating region of the device element being exercised in the test.
Although the process just described defines the speed path failures for the element being tested, it does not isolate the critical path within the element that is responsible for the error. In other words, the test resolution is limited. For example, if, say, the elements associated with the data cache are being tested, the critical path may be isolated to the load/store unit, or the cache memory itself. However, to enable the designers to expeditiously implement performance improvements, there is a need in the art for test systems and methods that increase the resolution of the critical path identification.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
The aforementioned needs are addressed by the present invention. Accordingly, there is provided, in a first form, a method for testing semiconductor devices. The method sequentially drives a first set of pattern vectors on a device under test (DUT). A first predetermined vector of the set of pattern vectors constitutes a pattern vector under test. A trigger signal having a first value is output in association with the sequential driving of the first set of pattern vectors. If a pattern vector other than the first predetermined vector fails, a second set of pattern vectors is sequentially driven on the DUT, in which a second predetermined vector of the second set of pattern vectors comprises the pattern vector under test. A trigger signal having a second value is output in association with the sequential driving of the second set of pattern vectors.
There is additionally provided, in a second and third form, respectively, a computer program product and a data processing system for testing semiconductor devices. The program product includes instructions for performing the aforesaid method, and the data processing system contains circuitry operable for performing the method.